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Memory and bus architecture
RM0008
2
2.1
Memory and bus architecture
System architecture
In low-, medium- and high-density devices, the main system consists of:
●
Four masters:
–
–
Cortex?-M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 & 2 (general-purpose DMA)
●
Four slaves:
–
–
–
–
Internal SRAM
Internal Flash memory
FSMC
AHB to APB bridges (AHB2APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1 :
Figure 1.
System architecture
ICode
DCode
FLITF
Flash
Cortex-M3
Sys tem
SRAM
DMA1
DMA
FSMC
SDIO
Ch.1
Ch.2
AHB system bus
Bridge 2
Ch.7
Reset & clock
control (RCC)
Bridge 1
APB2
APB 1
ADC1
GPIOC
DAC
SPI3/I2S
ADC2
GPIOD
PWR SPI2/I2S
DMA2
DMA Request
ADC3
USART1
SPI1
TIM1
TIM8
GPIOA
GPIOB
GPIOE
GPIOF
GPIOG
EXTI
AFIO
BKP IWDG
bxCAN WWDG
USB RTC
I2C2 TIM7
I2C1 TIM6
UART5 TIM5
UART4 TIM4
38/995
Ch.1
Ch.2
Ch.5
Doc ID 13902 Rev 9
DMA request
USART3 TIM3
USART2 TIM2
ai14800c
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